1. Field of the Invention
This invention relates to a differential phase shift keying demodulator.
2. Description of the Related Art
For a video signal recording apparatus, it is known to obtain a modulated data signal (hereinafter referred to as DPSK signal) by differential phase shift keying (DPSK) such a data signal, that represents a photographing data or some comments, with a frequency which is an integer times, for example 13 times, as high as a horizontal synchronizing signal, used as a carrier; and to frequency multiplex the modulated signal together with a video signal in recording the video signal.
FIG. 1 of the accompanying drawings shows the conventional circuit arrangement which is arranged to demodulate the above-stated DPSK signal. The circuit arrangement includes a synchronizing signal separating circuit 14; a timing pulse generating circuit 15; a shift register 16; an exclusive OR gate 17; a low-pass filter 18 (hereinafter referred to as LPF); and a latch circuit 19. A terminal 1 is arranged to receive the DPSK signal; a terminal 2 to receive clock pulses; and another terminal 3 to receive a video signal with which the DPSK signal is synchronized. With these signals respectively supplied to these input terminals, an exclusive logical sum of the DPSK signal, which is delayed by the shift register 16, and the DPSK signal which is not delayed is produced at the putput of the exclusive OR gate 17. Phase detection is thus carried out. A detection signal which is thus obtained is supplied to the LPF 18 to have the carrier component thereof removed. The output of the LPF 18 is latched at the latch circuit 19. Then, in accordance with timing pulses coming from the timing pulse generating circuit 15, a demodulated data signal is produced from a terminal 4 at every one data bit transmitting period.
The conventional demodulator which is arranged in this manner has presented a problem in arranging it into an IC, because a portion of it including the LPF 18 must be externally arranged. This increases the size of the circuit and results in an increase in the price of the demodulator.
Further, in cases where an adverse effect of external noises comes to appear at a timing for latching, it sometimes becomes difficult to accurately demodulate the modulated signal.